The present invention relates, in general, to integrated circuits and, more specifically, to the design of integrated circuits having multiple Test Access Port (TAP) interfaces, a novel circuit, method of and program product for designing such circuits.
Test Access Port (TAP) interfaces are used to perform test and debug operations on a circuit. A TAP includes an instruction register, at least one data register, and a test bus which includes a Test Clock input (TCK), a Test Mode Select (TMS) input, a Test Reset input (TRSTN), a Test Data Input (TDI) and a Test Data Output (TDO). A simple serial protocol, such as the IEEE 1149.1 protocol illustrated in FIG. 5, is used to access the various test and instruction registers in a TAP.
Most integrated circuits require only one TAP. However, there are a number of situations in which more than one TAP are present on a chip. Embedded processor cores often include debug registers that can be accessed through a TAP under the control of a software development system. More than one such embedded core can be used on the same chip. Most current software development systems assume that all TAPs are connected in a daisy-chain fashion in which the TDI of each TAP is connected to the TDO of the preceding TAP in the chain. The TDI of the first TAP in a chain is connected to the TDI of the circuit and the TDO of the last TAP in a chain is connected to the TDO of the circuit. The TAPs share the test clock input, the TMS input and the TRSTN input. An additional TAP is usually required to control all circuit test operations and a Boundary Scan test data register. However, in other situations, test data registers might need to be shared.
These TAPs are preferably controlled from the same test bus such as the IEEE 1149.1 standard. The circuit as a whole should be compliant with the standard. It is also necessary to ensure that all of these TAPs are connected in a way that is compatible with existing software development systems. Another constraint is that existing TAPs usually cannot be modified to accommodate a specific circuit context.
Several techniques have been proposed to handle the presence of several TAPs in a circuit. In a paper entitled xe2x80x9cAn IEEE 1149.1 Based Test Access Architecture for ICs With Embedded Coresxe2x80x9d, IEEE International Test Conference, 1997, pp. 69-78, incorporated herein by reference, Whetsel L. proposes three techniques. The first technique consists of connecting the TAPs in a single daisy-chain. This technique results in a circuit which is not compliant with the standard. The second technique consists of selecting the TAPs using compliance enable inputs of the circuit. One combination of inputs selects the TAP that is responsible for all boundary scan operations related to the standard. This method requires additional inputs beyond of the five inputs required by the standard and the number of inputs increases with the number of TAPs. These inputs are not compatible with most software development systems. The third technique, which is also described in Whetsel U.S. Pat. No. 6,073,254 granted on Jun. 6, 2000 for xe2x80x9cSelectively Accessing Test Access Ports in a Multiple Test Access Port Environmentxe2x80x9d, incorporated herein by reference, provides a register for performing data transfer operations between the test bus and the TAPs. The method requires modification of the existing TAPs to generate a select output connected to the register and to accept an enable output generated by the register. Clearly, none of these methods meet the constraints set out earlier.
Oakland (Oakland S., xe2x80x9cConsiderations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuitsxe2x80x9d, IEEE International Test Conference, 2000, pp. 628-637), incorporated herein by reference, proposes two variations of the same technique. While the technique meets the constraints mentioned earlier, it possesses a number of limitations that are not desirable. According to the first variation of the technique, whenever an instruction needs to be shifted into any of the TAPs, the instruction register of all TAPs are concatenated to form a single instruction. The length of the instructions to be shifted in can become excessively long. Also, it is not possible to perform a structural test of the embedded TAPs. Finally, it is very difficult to diagnose problems because the instruction register is distributed throughout the chip. The second variation of the technique addresses the last two limitations by providing shadow registers for all instruction registers of the embedded TAPs. However, it is not possible to access the information captured by the instruction registers of the embedded TAPs during the Capture-IR state. There is also an additional cost in silicon area due to the shadow registers.
The present invention seeks to provide a novel, multiple TAP circuit architecture and a method of designing a circuit containing a plurality of TAPs which is compliant with the standard, which does not require modification of any of the embedded TAPs and which can be structurally tested, any which can effectively control any or all of the TAPs without the need for non-standard signals.
The present invention provides a Master TAP which functions as the circuit test bus for controlling data transfer operations with the remaining, secondary TAPs in the circuit. The secondary TAPs are connected between the circuit TDI and circuit TDO in one or more TAP groups. A selection code, stored in the Master TAP instruction register and loaded with each instruction, specifies the next TAP group which will be involved in a data transfer operation. A TDO selector responds to the selection code by connecting the group TDO of the specified group to the circuit TDO. A group TDI selector is provided for each secondary TAP group. The group TDI selectors are responsive to a shift state signal and operate to connect either the circuit TDI or the output of a padding register to the group TDI of their associated TAP group. The Master TAP produces a TMS signal for each TAP group under the control of the selection code. The TAP group specified by the selection code receives the TMS pulses applied to the circuit TMS pin. The remaining TAP groups receive an inactive TMS signal and are, thus, kept inactive. Except for connecting their test interface connections to the output of the Master TAP, none of the existing TAPs require any modification to accommodate the present invention. To simplify instruction loading operations, the length of the TDI-TDO path through each TAP group is the same for all groups, including the Master TAP group. The padding register may form part of the Master TAP instruction register or may be a separate register for each TAP group.
One aspect of the present invention is defined as a circuit having a plurality of Test Access Port interfaces, each interface having test connections including a Test Data Input a Test Data Output a Test Mode Select input, a Test Clock Input and a Test Reset input an instruction register and at least one test data register, comprising: one of the TAPs having test connections serving as a circuit test interface, the one TAP having: an instruction register having a length equal to the length of the longest instruction register plus a predetermined number of bits for storing a TAP selection code for selecting one of the TAPs; a TDO circuit responsive to the TAP selection code for selectively connecting the TDO of one of the TAPs to the circuit TDO; and the one TAP further including, for each other TAP in the circuit: a padding register having a length equal to the length of the instruction register of the one TAP less the length of the instruction register of the each other TAP and having an input connected to the circuit TDI, and an output; a TMS circuit responsive to a predetermined TAP selection code associated with the each other TAP and a TMS signal applied to a circuit TMS input for producing a TAP TMS signal for the each other TAP; and a TDI circuit responsive to a shift state signal for selectively connecting the TDI of the other TAP to the circuit TDI or to the output of the padding register.
Another aspect of the present invention is defined as a method of designing a circuit containing a plurality of Test Access Port interfaces, each the TAP having a Test Data Input a Test Data Output a Test Mode Select input, a Test Clock Input and a Test Reset input, an instruction register and at least one test data register, the method comprising the steps of providing a master TAP for at least controlling data transfer operations with other TAPs in the circuit; connecting master TAP test inputs and output to corresponding circuit test inputs and outputs; adding to the master TAP, an instruction register having a length equal to the length of the longest instruction register of each other TAP plus a predetermined number of bits for storing a TAP selection code for selecting one of the TAPs; a TDO circuit responsive to the TAP selection code for selectively connecting the TDO of one of the TAPs to the circuit TDO; and for each other TAP: adding a padding register having a length equal to the length of the instruction register of the master TAP less the length of the instruction register of the each other TAP and having an input connected to the circuit TDI, and an output; adding a TMS circuit responsive to a predetermined TAP selection code of the each other TAP for gating TMS pulses applied to the circuit TMS input to the each other TAP; adding a TDI circuit responsive to a shift state signal for connecting the TAP TDI to either the circuit TDI and or the output of the padding register.
A further aspect of the present invention is defined as a method of controlling or using a circuit having a plurality of Test Access Port interfaces in which one of the TAPs is connected to circuit test inputs and outputs and each the TAP interface includes a TAP Test Data Input a TAP Test Data Output a TAP Test Mode Select input, a TAP clock input and a TAP reset input an instruction register and at least one test data register, comprising: (a) loading each test instruction into the instruction register of the one of the TAPs, each instruction including a TAP selection code specifying the TAP to be accessed in the next instruction; (b) connecting the TDO of the TAP having a predetermined TAP selection code corresponding to the TAP selection code stored in the instruction register to the TDO of the circuit; (c) connecting the TAP TDI of all TAPs to the circuit TDI when accessing a test data register of a TAP; (d) connecting the TAP TDI of all TAPs to a serial output of respective padding register when the instruction register of a TAP is to be accessed; and (e) applying a sufficient number of clock cycles to shift data into the test data register or an instruction into the instruction register of the specified TAP; and (f) repeating steps (a)-(f) for each additional data transfer operation.